1. Field of the Invention
The invention relates in general to an integrated circuit, and more particularly to an integrated circuit including a test clock generating circuit.
2. Description of the Related Art
As designed and manufactured, digital logic circuits requires a suitable apparatus for circuit debugging and testing. A common digital logic circuit, as shown in FIG. 1 includes combinational logic circuits and sequential circuits. The combinational logic circuits 10˜16 generate output signals according to the present input signal. The sequential circuits, such as the flip-flops D1˜D6, can memorize and generate output signals according to the previous input signal, wherein the scan-chain signal sclk is a test clock signal.
The conventional method for testing a digital logic circuit is to serially couple a plurality of flip-flops as a scan chain. By doing this, the digital logic circuit can be debugged by recording specific logic values in the scan chain in order. This method is also called a scan test. The circuit can be selected to operate in a shift mode or a normal mode according to a plurality of multiplexers mu1˜mux6, and scan enable signals SE. When the circuit is operated in the shift mode (SE=1), the test pattern is scanned in from the tester and stored in the flip-flops D1˜D6. Afterwards, when the circuit enters the normal mode (or called capture mode) (SE=0), the values stored in the flip-flops D1˜D6 are sent to the combinational logic circuits 10˜16 to simulate the logic calculation under normal operational conditions, and the calculation results are stored in each flip-flop D1˜D6. Lastly, the circuit enters the shift mode again where the test results can be scanned out in order by the serially coupled flip-flop scan chain so as to check whether the function of the chip is normal or not.
In these few years, the operational clock loading of the chip has largely been enhanced from several tens MHz to several hundreds MHz, however, the chip cannot still be tested at speed for the scan clock provided by the tester is not enhanced accordingly. Even there are a few new testers, which can provide high-speed (at-speed) clocks, their cost in present is still expensive, thereby not meeting the cost benefit. Moreover, when the operational frequency of the interior circuits of the chip is faster than that of the input/output (I/O) circuit of the chip, it is difficult to test the chip at speed because the I/O circuit of the chip cannot operate normally in the high-speed (at speed) clock.